Issue Date: July 9, 2007
Materials In Motion
IN JUNE 2006, the semiconductor maker Texas Instruments unveiled details of the manufacturing process it would use to make its next generation of logic-type microprocessors, chips with circuit lines as small as 45-nm wide. The company revealed new circuit-line lithography and insulating techniques but said it wouldn't move to new and more complex high-dielectric-constant, or "high-k," materials in the chips' transistors.
One year later, TI changed its mind. Last month, the company announced it would in fact use high-k dielectrics in some of its new logic chips. Judy Shaw, the firm's manager of process engineering, explains that TI "overcame some of the hurdles that were preventing a transition to high-k for our most advanced, high-performance process."
TI's change of strategy illustrates the uncertainty pervading the semiconductor world as chip architecture continues to evolve to smaller and smaller dimensions, just as Gordon Moore said it would. His 1965 prediction, known as Moore's Law, holds that the number of transistors in a computer chip will double every two years.
The industry has held to Moore's Law for more than four decades now, but in the past few years, doing so has required moving beyond silicon and a few core chip-making materials to a multiplicity of new and exotic elements. "We're spreading ourselves across the periodic table," says Peter N. Heys, research and development director at SAFC Hitech, the performance materials business of Sigma-Aldrich's SAFC division.
In the case of high-k materials, one of the new elements is hafnium. For decades, the semiconductor industry used silicon dioxide as its transistor gate insulator, the thin film that separates the gate, which turns current flow on and off, from the channel through which the current flows. SiO2 has a dielectric constant of 4.2.
As chip size shrinks, the gate oxide must be made thinner and thinner to maintain adequate performance. But below 2 nm or so, the gate oxide becomes so thin that electrons can leak through and sap power from the device. Hafnium oxide has a higher dielectric constant, or k value, than SiO2 and can be applied as a thicker film that blocks electron leakage while maintaining performance.
Although semiconductor companies have been studying hafnium oxide for a decade or more, they have been hesitant to take the plunge. That's because SiO2 can be formed on top of a silicon wafer, the surface on which chips are built upon, by simple thermal oxidation. "The SiO2 interface is a beautiful interface with few problems, and that can't easily be obtained with hafnium oxide," says Egbert Woelk, director of metalorganics marketing at Rohm and Haas Electronic Materials.
HAFNIUM OXIDE, Woelk notes, has to be applied through sophisticated techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). And because hafnium isn't compatible with conventional silicon gate electrodes, incorporating it requires the use of novel metals as gate electrodes.
It was owing to such complexities that TI originally held off, and even the industry's International Technology Roadmap for Semiconductors didn't predict introduction of high-k materials until 2010. So it came as a surprise in February when Intel and IBM, two of the semiconductor industry's research leaders and major contributors to the roadmap, announced the imminent adoption of hafnium oxide dielectrics. Japan's NEC has also backed hafnium.
Researchers have long called for hafnium-based materials to be introduced in 45-nm semiconductors, says Gary Miner, chief technology officer of the front end products group at Applied Materials, a leading maker of CVD and ALD equipment. "The big skepticism was whether anyone could get it done in high-volume manufacturing."
While semiconductor makers are confident that they can, in fact, do it, the fun is just beginning for the materials companies such as SAFC Hitech, Rohm and Haas, and Air Products & Chemicals that serve them. That's because these firms must now perfect the development of hafnium-containing precursor compounds that their customers can easily deploy.
As Heys explains, CVD and ALD of metal-containing materials generally involve the vapor-phase deposition of an organometallic precursor. Its ligands dissociate upon contact with the hot silicon wafer, leaving a metal-based film. This precursor, Heys notes, has traditionally been a gas. "Now with hafnium, they are liquids and in some cases even a solid," he says. "The trick is to get the liquid or solid into the vapor state."
Intel, IBM, and other logic chip firms are looking to their materials suppliers for expertise in designing dielectric precursors. In response, companies such as SAFC Hitech and Rohm and Haas are drawing on their experience with manufacturers of memory chips, a segment of the semiconductor business that has already transitioned to high-k materials.
The switch started several years ago, when memory chip makers introduced aluminum oxide, a dielectric with a k value of about 8.0, based on the precursor trimethylaluminum. As memory devices shrank, dielectric requirements escalated, and by 2005, higher-k hafnium-based materials were being introduced.
SAFC Hitech's Heys says his firm has become a major supplier of hafnium amides as precursors to hafnium oxide for memory devices. Likewise, Woelk calls Rohm and Haas the market leader in tetrakis(ethylmethylamino)hafnium, thanks to a joint venture with South Korea's UP Chemical. "Hafnium is coming into full swing in memory, and we are in the midst of it," he says.
Hafnium-containing logic chips, the powerful heart of personal computers and many electronic devices, will roll out of semiconductor factories later this year, in the case of Intel, and in 2008, for IBM and TI. Yet the exact composition of the high-k materials is not always clear.
IBM and Intel have stated only that their 45-nm gates will contain hafnium. TI, in contrast, disclosed last month that its gate insulator will be hafnium silicon oxynitride, or HfSiON, formed by depositing hafnium silicon oxide and then reacting it with nitrogen plasma. According to Applied Materials' Miner, the higher the hafnium content, the higher the k value. Thus, pure hafnium oxide has a k value of about 30 but is a challenging material to integrate into a semiconductor. Silicon-containing compounds such as HfSiON have a lower k value but are easier to integrate.
ALTHOUGH DETAILS are still emerging about the new high-k compounds, chemical companies are already looking at next-generation precursor materials. SAFC Hitech, for example, is promoting a number of hafnium and zirconium compounds featuring cyclopentadienyl groups. It claims that the new precursors perform at higher temperatures than the hafnium amides without the onset of decomposition.
In March, Rohm and Haas signed an agreement with Harvard University's office of technology development to license a new class of metal amidinate compounds useful for making thin high-k and metal films. The amidinates, from the lab of Harvard thin-film chemist Roy Gordon, overcome stability issues encountered with the hafnium amides, Woelk says.
In addition to improved performance for customers, these new materials offer patent protection for their manufacturers. As such, they promise higher profits than do compounds such as the amides, which are produced by a number of competitors. Indeed, even though the high-k materials field is technologically daunting, it's being pursued by a sizable number of materials suppliers. In addition to SAFC Hitech and Rohm and Haas, market participants include Praxair Electronics, Air Products, ATMI, and Air Liquide.
Dan O'Connell, director of advanced integration materials at Air Products, says his company started high-k joint development projects with customers as early as 2000 and continues to be actively involved. Yet he acknowledges that the field is crowded. "I can understand companies that are struggling with the proposition of this one material sale," he says.
But for Air Products, O'Connell points out, high-k precursors are part of a suite of products sold to the semiconductor industry that includes equipment used to deliver precursors as well as ancillary chemicals, such as cleaning mixtures and photoresist strippers, formulated to complement the new high-k materials. "The change to a metal gate is going to require a whole lot of changes in processes beyond that," he says. "That plays to our strengths."
Air Products isn't the only company pursuing the market for ancillary materials. According to Woelk, for example, Rohm and Haas is researching organometallic compounds that can deposit ruthenium metal connectors onto the high-k dielectric gate. It's also developing titanium and other barrier layer materials that can be sandwiched between the new dielectric and copper circuitry to block unwanted chemical reactions that can compromise the long-term stability of an electronic device.
Another strength that Air Products claims is its dominance of the market for precursors to low-k dielectrics, which are the insulating materials deposited between the closely spaced circuit lines in a computer chip to prevent electrical cross-talk. In the same way that 2007 is the year for touting high-k plans, 2006 was the year for low-k announcements, and most chip companies vindicated an approach championed by Air Products.
Those announcements were the culmination of several years of jockeying among materials companies to become preferred low-k suppliers. Firms including Dow Chemical, Air Products, Rohm and Haas, JSR Micro, and Honeywell all claimed to have solutions for computer chip makers that wanted to lower the dielectric constant of their insulating materials.
FOR MOST of the chip industry's history, circuit lines were insulated with SiO2, the same ubiquitous material long used as the gate insulator in transistors. But just as the shrinkage in transistor geometry spurred the need for a higher k material, more closely packed circuit lines demanded a lower k material.
Hichem M'Saad, vice president and general manager of Applied Materials' blanket dielectric films division, explains that the 130-nm-wide circuit lines that were leading-edge in 2001 were insulated with fluorinated silicate glass, a transitional material made by infusing traditional SiO2 with a fluorinated compound such as silicon tetrafluoride.
True low-k materials debuted with later-generation chips that feature circuit line widths of 90 nm and 65 nm, he says. Still in widespread use, they are carbon-doped silicon oxides formed from precursors such as trimethylsilane or tetramethylcyclotetrasiloxane. Deposited on the silicon wafer through CVD techniques, they have a k value of about 3.0.
Although CVD techniques prevailed through those generations of chips, it was not for lack of competition from purveyors of an alternative class of dielectric that is spun onto the silicon wafer in much the same way that photoresists are applied to make the circuit lines themselves. Backers of spin-on low-k technology were counting on finally winning customers when line widths shrank further to 45 nm, but the evidence is that they have not succeeded.
TI and IBM announced separately last year that they would use a porous "ultra-low-k" dielectric in their 45-nm chips. Although O'Connell won't name names, the terminology used by the chip companies indicates that they are adopting chemistry championed by Air Products. "This is the new dielectric technology for high-performance 45-nm chips," he says. "Otherwise, it will be continued use of existing dielectric materials." Industry sources say Intel, the world's leading chip maker, is sticking with the nonporous carbon-doped oxide it employed in earlier chip generations.
Air Products calls its system PDEMS, for porous diethoxymethylsilane. Using CVD, the precursor diethoxymethylsilane and an organic porogen, or pore-generating material, such as α-terpinene are vaporized and co-deposited on a circuit-line-covered silicon wafer. The resulting film is subjected to ultraviolet curing, during which the porogen burns off, leaving air-filled holes. Air, O'Connell points out, has a dielectric constant of 1.0, bringing the k value of the porous insulating film down to below 2.5.
Although the chemistry is Air Products', the company can't take all the credit for its adoption by the semiconductor industry. CVD equipment makers, notably Applied Materials, played a big role in promoting it to their customers in an effort to extend carbon-doped oxide technology and to keep them from migrating to competing spin-on chemistry and equipment.
Applied Materials' M'Saad says that his firm has, so far, captured the entire market for the CVD equipment used to apply ultra-low-k films, which it sells under the name Black Diamond II. "It's not just about the precursor," he says. "The added value we bring is our own way of making sure the film is integrated into the structure without any problems for the customer."
Both Applied Materials and Air Products are working to advance PDEMS-type technology to the next generation of chips, the 32-nm devices expected to debut in 2009 from Intel and a year or two later from other semiconductor firms. M'Saad says slight tweaks in chemistry will be involved, while O'Connell anticipates the use of "k restoration," a technique for restoring the k value of a dielectric that may have been compromised by subsequent chip fabrication steps.
Proponents of spin-on dielectrics may be down, but they do not see themselves as out. Maria Peterson, emerging products program director at JSR Micro, acknowledges that CVD has been the dominant technology so far. Yet, she says, JSR's polymeric spin-on dielectrics, based on methylsilsesquioxane, are being used in 65-nm devices, and she expects further adoption for 45-nm devices and beyond. "It has started, and there is real business," she says.
Peterson points out that the porogen-burning step required by PDEMS-type systems can leave a film in the CVD equipment that, at best, requires careful cleaning and, at worst, can contaminate the delicate lens used to project circuit-line patterns on the silicon-wafer surface. In contrast, she claims, JSR's spin-on materials can easily achieve a k value of 2.2 with little or no porogen. Spin-on materials are also good at filling challenging high-aspect-ratio gaps in the chip architecture, she says.
JSR is actively exchanging chemical, process, and integration know-how with leading-edge semiconductor companies developing 45-nm devices, Peterson says. And the company is also targeting 32-nm devices, where she expects further inroads by spin-on materials.
The next-generation 32-nm chip is the sole focus of market development efforts at photoresist suppliers, another key family of materials companies. As Rick Hemond, Rohm and Haas's marketing director for microelectronic technologies, explains, "45 nm has come and gone and is locked at the world's top device makers. Those material choices have been made."
Resist makers like Rohm and Haas have succeeded in adapting photosensitive methacrylate polymers to work in 90-, 65-, and 45-nm devices. Now, they are feverishly working to extend the chemistry yet one more generation to help their customers stave off the introduction of a still largely untested lithographic technology based on extreme ultraviolet light, or EUV.
This will be no easy task, because lithography equipment and materials companies already have had to pull one bold new trick from their sleeves to make their systems work at 45 nm.
Industry executives explain that, for 90- and 65-nm chips, lithography is a relatively straightforward process by which the polymer-based resist is spun onto a silicon wafer and then patterned with 193-nm wavelength light shone through a photomask. Resist areas not shaded by the mask are chemically altered and easily etched away with solvents. Aluminum or copper is then deposited in the grooves that remain to create circuit lines.
Mark Thirsk, a former Rohm and Haas manager now with Boston-based Linx Consulting, notes that most chip makers are adding a layer of antireflective coating to the silicon wafer before spinning on the resist. The coating keeps incident light from bouncing off the underlying silicon and degrading the image captured in the thin bands of undeveloped photoresist.
THE BIG CHANGE in making 45-nm chips will be the introduction of immersion lithography, in which the resist and the projecting lens are immersed in ultrapure water. Because water has a refractive index of 1.44, versus 1.0 for air, the effective wavelength of the light coming through the photomask is reduced to about 132 nm, and thinner lines can be drawn.
IBM and TI announced the adoption of immersion lithography last year at the same time that they disclosed their low-k dielectric choice. Intel, notoriously cautious about embracing new technology, is using traditional techniques for 45-nm chips. Heather Banisaukas, an engineer from Intel's Hillsboro, Ore., facility, told a semiconductor manufacturing conference in Italy last month that the company expects a 27% cost savings from sticking with dry lithography.
Indeed, dunking the silicon wafer into water can introduce complications. The main ones, according to Mark Slezak, senior technical manager at JSR Micro, are that the water can penetrate the resist and that resist components can leach into the water, possibly damaging the projecting lens. The main solution so far, Slezak says, has been to add a topcoat polymer that helps prevent leaching and control the surface tension of the water-lens-resist interface.
Although this topcoat does the job, it adds yet one more step to a process that for semiconductor makers is becoming disturbingly complex. At 45 nm, notes Ralph Dammel, vice president of global technology at AZ Electronic Materials, some companies are already putting down four layers in the lithographic process: a high-carbon-content planarizing coating to create a smooth foundation, a silicon-containing antireflective coating, the photoresist, and then the topcoat. He expects this combination to become the industry standard.
According to Rohm and Haas's Hemond, one attempt to cut a step is to use an in situ topcoat, or what Rohm and Haas calls an embedded barrier layer. Mixed into the photoresist, this polymeric material migrates to the top of the resist during the spin-on process, leaving an ultrathin barrier layer. Once there, Hemond says, the material prevents leaching while optimizing the contact angle between the water and the photoresist for maximum resolution during light projection.
In situ topcoats are not yet used in commercial production, and industry players are debating whether they will be, or should be, for 32-nm chips. For example, although JSR is developing in situ topcoats, Slezak makes the case for a separately applied topcoat because it creates a constant water/resist interface for every imaged layer independent of the actual resist being used. Still, AZ's Dammel says he "would venture a prediction that the industry will completely move to in situ topcoats eventually."
IN GENERAL, there is much uncertainty about lithography at 32 nm and many conflicting opinions about which techniques will prevail. Linx's Thirsk lays out three possibilities: extension of current 193-nm lithography with a technique known as double patterning; extension with immersion fluids that have a higher refractive index than water; and transition to EUV, a completely new lithographic technique that will require new resists and new equipment for projecting EUV light emitted from molten tin.
Thirsk and other industry players doubt that EUV will be ready by 2009 or 2010, when leading-edge semiconductor makers will be ramping up production of 32-nm chips. For one thing, only two production prototype light-projecting tools are available in the industry worldwide, and both have reliability issues, he says. And everyone in the industry remembers the years and millions of dollars invested in developing resists for lithography based on 157-nm light. Once expected to debut in 45-nm devices, the technology was rejected by Intel and others in 2004 due to concerns about the production-worthiness of the light-projecting equipment.
High-index immersion has both backers and detractors. JSR, for example, has been promoting its Solonx system, which includes a resist, a topcoat, and an organic high-index liquid that has a refractive index of 1.64, versus 1.44 for water. Equipment makers, meanwhile, are working on a new projection lens, based on lutetium aluminum garnet, that will complement the high-refractive index of the new fluids.
Rohm and Haas's Hemond acknowledges that high-index immersion is technically elegant, but he expects it to be complex and expensive as well. Spent water, after all, can be sent down the drain in the current immersion process, whereas an organic fluid would have to be recycled. "It will be another cost, another unknown, another risk for customers who don't like to take risks," he says. "I believe people will use water as long as they can."
Most photoresist executives are betting on double patterning as the likely path forward. "Since both EUV and high-index immersion are going to be late for 32 nm, the field will move to double patterning by default," says AZ's Dammel. But the path to double patterning is strewn with its own roadblocks and potential dead ends.
Hemond explains that double patterning is a generic phrase used to indicate lithographic schemes in which a complex pattern is broken into two less complex patterns and then recombined on the silicon wafer. One version of double patterning uses conventional resists that are exposed twice and etched twice in a seven-step process. Conventional single-exposure lithography requires just two steps.
A second version is the dual-exposure, single-etch approach. Semiconductor makers are enthusiastic about this method because it requires fewer processing steps; the challenge for resist manufacturers is to develop a technique to expose the second resist pattern without harming the first pattern. Slezak, for example, says JSR is looking into cross-linking or chemical freezing agents that would fix the first pattern prior to the second exposure.
The uncertainty about lithography at 32 nm presents a conundrum for resist manufacturers, Hemond notes, because they can't afford to pursue all possible avenues of research. "I picture it as a neighborhood with a lot of cul-de-sacs," he says. "You don't want to get lost in them." Rohm and Haas tries to limit its wrong turns by concentrating its R&D resources on alliances with a few industry leaders.
Dammel laments the fact that materials suppliers have not adopted the precompetitive consortia and other cooperative research approaches that their customers have. "We see that semiconductor manufacturers increasingly cooperate in development and combine their efforts to save costs," he observes. "Materials suppliers have not done so and do not have a business model for doing so."
Meanwhile, the cost of development isn't abating. Hemond says Rohm and Haas has invested $100 million in its electronic materials business over the past three years. And the company just announced that it will spend $60 million on new lithography equipment to research 193-nm resists and antireflective coatings.
Because such pricey investments will be required to develop the materials of the future, Hemond sees a consolidation of the electronic chemicals industry into just a few strong players. He cites a rule of thumb holding that, over time, industries consolidate into three major players. "The rule of three applies in most businesses and will in photoresist materials," he says. "We expect to be one of those three."
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