The prediction that the number of components on semiconductor chips will double every two years—known as Moore's Law after Gordon E. Moore, the Intel cofounder who made the prediction in 1965—has turned out to be remarkably prescient in its first 40 years. But given the technological and economic challenges of fabricating semiconductors so small that the placement of individual atoms is becoming critical, can Moore's law hold up much longer?
Experts speaking at a conference organized by DuPont at the Semicon West semiconductor fabrication trade show in San Francisco last month maintained that Moore's law has a lot of life left in it. But its continuation, they said, will require that the semiconductor industry familiarize itself with increasingly exotic materials and ideas.
The semiconductor industry thinks in terms of "nodes" that describe the smallest features on a chip. Today's vanguard is the 90-nm node, though industry leader Intel has been producing 65-nm-based chips since late last year. The technologies needed for the 65-nm node are well-defined. At DuPont's conference, industry experts discussed the technologies that will emerge for the 45-nm node and beyond.
Larry F. Thompson, president of the semiconductor materials and equipment consulting firm Intellectual Property Services & Solutions and former R&D manager with Bell Laboratories, outlined future challenges for lithography, a technology in which laser light is used to pattern circuit lines on a silicon wafer.
The 193-nm-wavelength light used to make 90-nm and 65-nm chips is expected to be used again at 45 nm, with the change that the projection lens will be immersed in water or another fluid to enhance resolution. One possible complication, Thompson said, is the creation of unwanted bubbles as gases leach from the photoresist. But, he added, immersion lithography may last up to four nodes "if the material community can come up with some of the solutions required to achieve the ultimate achievable resolution."
Next in line after 193-nm immersion technology is extreme ultraviolet (EUV) lithography. Thompson said one of the major challenges is that available lasers aren't nearly powerful enough for EUV imaging. Patterning lasers would need to put out as much as 300 W for the technology to be rolled out, and only a fraction of that is available today. "An epiphany has to happen," he said. "I don't believe in miracles in science."
Thompson said the economic pressures of making ultrasmall components may prove more challenging than the technical ones. Airplane speed steadily increased in the first few decades after the Wright brothers' flight, he noted, but commercial airlines still travel at below the speed of sound because supersonic planes, SSTs such as the Concorde, were economic failures.
If you look at all industries, they mature on the parameter you are tracking because of economics, he said. "The SST of our industry is EUV lithography."
Robert H. Havemann, vice president of process integration and applications for Novellus Systems, a maker of semiconductor fabrication equipment, outlined future materials for chip circuit lines, or interconnects. He said there will be an increasing need for low-dielectric-constant (low-k) insulators, which prevent "cross talk" as interconnects get smaller and closer together.
Fluorinated silicate glass, which has a k value of about 3.6, was used on the 130-nm node, while early low-k materials with k at about 3.0 are being used for the 90-nm and 65-nm nodes.
Havemann said the 45-nm node will likely use porous low-k systems, a technology whereby pores of air, which has a dielectric constant of about 1.0, are introduced into the insulator to lower its overall k value to about 2.5. At the 32-nm node, he said, the dielectric constants of these materials will have to be brought below 2.5. However, introducing more and more pores into the material undermines its ability to mechanically stand up to subsequent wafer-processing steps such as chemical-mechanical planarization.
According to Havemann, substantial progress has been made on porous low-k dielectrics. "This has been on the road map for many years, and the industry may finally have it right," he said.
For future nodes, the challenges haven't been worked out as well, Havemann acknowledged. "Moving forward, say beyond 32 nm, it gets really murky to see what materials might be used, because we are really starting to count atoms when we get to those regimes," he said. "We are nearing the physical limits of what we can do with the interconnects. A k of 1 is as low as you can go."
Entirely new technologies will come into play as components become smaller, said Daniel J. Herr, Semiconductor Research Corp.'s director of nanomanufacturing science research. He showed a picture of an experimental 6-nm gate but pointed out the impossibility, given their small scale, of manufacturing such devices uniformly. "It will never be manufactured because you can never make two of them the same," he said. Directed self-assembly, he said, may someday address these problems and augment EUV as a way to draw small features on the semiconductor.
Herr added that semiconductor companies may borrow ideas from biology to extend the functionality of their products. "This organ we call the brain is a wonderful image recognition and image capture tool," he said. "Part of our challenge is to look at parallels with biological systems and see what we can draw into our community."
The semiconductor industry needs to be open minded if it is to extend Moore's law after its conventional materials are pushed to their technical limits. "We should start comprehending more and more into our road map," Herr said. "What I mean by that is: How do you add functionality to the system using perhaps nonlinear materials, not just digital systems? That's a playground we haven't played in."