A Tiny Problem

During a visit by President Barack Obama in February, Intel executives announced plans to build a new semiconductor facility in Chandler, Ariz. To cost more than $5 billion, the plant will be the most advanced high-volume semiconductor “fab” in the world, Intel said, making chips with features as small as 14 nm wide.

For President Obama, the announcement demonstrated that American manufacturing is alive and well; for Intel, it was proof of continued technological superiority. Not in the company’s press release, though, was the fact that Intel won’t be harnessing lithography based on extreme ultraviolet (EUV) light to create those tiny features, as industry watchers had once expected. Instead, the computing giant will extend 193-nm light lithography for yet one more generation of semiconductor.

Intel and its competitors are falling back on 193 nm for their most advanced chips because, despite years of effort and hundreds of millions of dollars of investment, EUV lithography isn’t ready for commercial manufacturing. Its key shortcoming is the lack of a steady, consistent light source that holds up under production conditions.

Fortunately for the chip industry, researchers at electronic materials and lithography tool companies have been diligently tweaking and massaging 193-nm technology to extend it much further than anyone had expected it could go. Yet even these scientists acknowledge that such stopgap measures are complicated, expensive, and not likely to work for much longer.

“Everyone is surprised at how well 193 has done,” says Mark Thirsk, a former materials company manager who is now a managing partner with the electronic materials market research firm Linx Consulting. “It’s not desperation, but it’s creativity in a difficult situation.”

Advances in semiconductor technology come in many forms, but the most critical one is arguably the shrinkage of circuitry and other features from one chip generation to another through improvements in lithography. It’s this scaling, more than any other advance, that has kept the industry true to Gordon Moore’s 1965 prediction, known as Moore’s law, that the number of transistors in a computer chip will double every two years.

In lithography, a polymer-based photoresist is spun onto a silicon wafer and then patterned with light shone through a photomask imprinted with features. Resist areas not shaded by the mask are chemically altered and easily etched away with solvents. Aluminum, copper, and other materials are then deposited into the resulting grooves to form transistors and other chip features.

Lithography based on 193-nm light created with an argon fluoride laser was introduced in 2004 to pattern 90-nm features. Semiconductor makers extended it without much trouble to make 65-nm features.

To get to the next generation of chip, with 45-nm features, some companies introduced immersion lithography, in which the resist and the projecting lens are immersed in ultrapure water. Because water has a refractive index of 1.44, versus 1.0 for air, the effective wavelength of the light coming through the photomask is reduced to about 132 nm, and thinner lines can be drawn. Immersion technology is also used in 32-nm chips, today’s most advanced.

As 193-nm lithography moved through successive chip generations, the photoresist—a methacrylate polymer decorated with various comonomers—has remained basically the same. All around it on the wafer, though, new and revamped photoresist ancillaries are finding a home.

One of the earliest ancillary materials, introduced about 15 years ago, is the bottom antireflective coating, or BARC. Containing chromophores to absorb light, BARC is applied below the photoresist to keep incident light from bouncing off the underlying silicon and degrading the surrounding undeveloped photoresist.

Firmly entrenched in conventional 193-nm lithography, BARCs take on an enhanced role with immersion lithography, notes Nick Pugliano, global marketing director at Dow Electronic Materials. Instead of a single layer, BARCs for immersion are often two layers—one might be organic and the other silicon based—to minimize reflectivity in the new aqueous medium.

Meanwhile, lying on top of the photoresist in advanced semiconductors is a layer known as a topcoat or top antireflective coating (TARC). Its function, explains Ralph R. Dammel, chief technology officer at AZ Electronic Materials, is to suppress a periodic variation in light absorption known as the swing curve.

Early TARCs contained perfluorooctane sulfonic acid (PFOS), which, unfortunately, was found to bioaccumulate in the environment. Working with customers, AZ created a TARC out of a tetrafluoroethylene-based polymer that doesn’t contain PFOS. The product quickly caught on. “We have a reasonable market share in BARCs, but in TARCs we are number one,” Dammel says.

Indeed, TARCs and other photoresist ancillaries have become AZ’s main area of lithographic research. Dammel says the company decided five years ago to stop developing cutting-edge photoresists and to focus instead on the ancillary materials.

Even with the help of ancillaries, the smallest feature size achievable with single-exposure 193-nm lithography is around 40 nm. Thus, in the absence of EUV, which has a wavelength of just 13.5 nm, the semiconductor industry has turned to yet another set of tricks to get to the 32-nm feature node and below. Known as multiple patterning, it’s a collection of techniques for doubling, tripling, or even quadrupling feature density by overlaying one lithographic pattern on top of another.

JSR Micro, the electronic materials arm of Japan’s JSR, is one of the world’s leading photoresist developers. Mark Slezak, the firm’s director of lithography technology, says multiple patterning represents the confluence of the best of lithographic science with a new spirit of cooperation among photomask designers, toolmakers, and materials suppliers.

“Previously, chip designers dictated the layout of the device, and we would struggle as a lithography community to meet the challenge,” he says. “Now, engineers are going to the designers, explaining their limitations with respect to physics, and working with them to optimize the layout so it is more lithography friendly.”

According to Slezak, three main variations on multiple patterning have emerged.

Makers of memory chips, which typically contain repetitive features, are drawn toward a technique called self-aligned double patterning. In this approach, lines of photoresist created with conventional lithography are coated with a silicon dioxide film that rises and falls over them in peaks and valleys. An etching step removes the film at its peaks and in the valleys, leaving only “sidewalls” clinging to the resist lines. Then, etching away resist lines leaves two sidewalls that are the starting point for feature doubling.

For logic chips, which boast two-dimensional features not amenable to the self-aligned approach, chip makers are pursuing a more conservative form of multiple patterning known as litho-etch, litho-etch. It involves patterning and etching two sets of features into a silicon wafer, one after the other. It’s straightforward, Slezak says, but involved: TARC, photoresist, and two underlayers are often applied twice to create the desired pattern.

JSR is a leading proponent of the third technique, called litho-freeze, litho-etch. In this approach, the first pattern is chemically or thermally “frozen” so that the second one can be applied without etching the first one, meaning fewer layers and etch steps.

The additional chemistry of litho-freeze, litho-etch aside, the advantage of multiple patterning, Slezak says, is that it involves known techniques, tools, and materials. “The semiconductor industry is conservative by nature,” he points out. “They try to go with what is known rather than what is unknown.”

But multiple patterning is complex and expensive. “Lithography at 193 nm has the ability to do some pretty amazing stuff, but the costs get horrendous,” Thirsk says. “You can do 14 or 22 nm with enough tricks and tweaks, but every time you do that you add costs.”

AZ and JSR, through alliances with IBM, are developing a technique called directed self-assembly, or DSA, that promises to extend 193-nm lithography even further—and with fewer process steps. In December 2010, AZ and IBM announced an agreement to develop self-assembling block copolymers for use in DSA. Then in March, at SPIE’s Advanced Lithography 2011 conference, JSR and IBM presented a paper on a three-year-old research agreement to develop DSA based on a special polymer blend rather than block copolymers.

At Dow, Pugliano expresses interest in DSA but has a wait-and-see attitude. As a major plastics manufacturer, Dow has plenty of experience with polymer self-assembly, he notes. But Dow is looking ahead to EUV and focusing on improving the photospeed, resolving power, and pattern fidelity of photoresists that will work in EUV light.

Unlike the relatively pure 193-nm light that comes out of an argon fluoride laser, Pugliano notes, the 13.5-nm light, created by firing a CO₂ laser at drops of tin, is spectrally impure. “Making the resist particularly sensitive to the 13.5-nm EUV photon while spectrally filtering the longer wavelength radiation is a key piece of photochemistry the industry is working on,” he says.

The resists that might be able to do this, experts say, include known photopolymers such as polyhydroxystyrene and methacrylates, as well as newer fluorinated polymers, molecular glasses, and nanoparticles. “All of these are still on the table,” JSR’s Slezak says.

They are on the table because EUV lithography continues to evolve. To date, only a handful of preproduction-strength EUV tools have been shipped to customers. Back in EUV development labs, engineers are still struggling to fine-tune the light source, ramp up power levels, and improve consistency and reliability.

Yet given the investments that have been made and the lack of alternatives for continuing to advance Moore’s law, most in the electronic materials sector are betting on EUV. “This is big science. The annual spending, and the technology challenge, is as big as putting a man on the moon,” Pugliano says. “It’s really hard stuff, but I believe it will succeed.”