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Electronic Materials

Mixing semiconductors could lead to 6G wireless devices

Bonding III-V circuits to silicon provides high-frequency performance potentially useful for next-gen connectivity

by Neil Savage, special to C&EN
May 18, 2022


An electron microscope image shows a cross section of a semiconductor device that has a thicker lower layer of silicon circuits, a middle layer of silicon dioxide and aluminum oxide dielectrics, and an upper layer made of III–V semiconductor materials.
Credit: ACS Nano
In the new device, a layer of dielectrics separates conventional silicon circuits from III-V semiconductor circuits bonded to the top.

Even though fifth-generation (5G) wireless technology has yet to fully take root around the world as the standard for mobile communications, researchers are already envisioning 6G wireless. This next step requires high radio frequencies in the range of several hundred gigahertz, compared to approximately 75 to 150 GHz for 5G. Devices with higher operating frequencies could use new portions of the radio spectrum and allow more data to be transmitted faster, allowing, for instance, quicker downloads of high-definition video.

To get there, a group of scientists in South Korea tried to combine the manufacturing ease of silicon with the high-frequency performance of compound semiconductors. They’ve stacked circuits made with these two types of materials together into a layered device with record-high radio frequency performance (ACS Nano 2022, DOI: 10.1021/acsnano.2c00334).

Silicon, used for years to make billions of computer chips, has never been beaten for low cost and ease of fabrication. It’s difficult, though, to coax silicon circuits to reach high radio frequencies. III-V compound semiconductors, so called for their position in the periodic table, such as indium gallium arsenide (InGaAs) can reach those higher frequencies because of how fast electrons can move inside them.

One possibility is to make the radio-frequency circuits—the parts of a device that transmit and receive signals—out of III-V materials and the other circuitry out of silicon. Building both on the same chip presents a problem, though, because the crystal lattices of the materials don’t match, and growing them together places strains on the chips.

Instead of building these circuits on the same substrate, Inyong Kwon of the Korea Atomic Energy Research Institute, SangHyeon Kim of the Korea Advanced Institute of Science and Technology, and their colleagues built radio-frequency transistors made of InGaAs separately and bonded them to the top of silicon circuitry. The researchers built the silicon and radio-frequency circuits starting with a silicon wafer and an indium phosphide wafer, respectively. By topping the silicon circuits with a dielectric layer of silicon dioxide, the team could shield currents from one wafer from interfering with currents in the other. Finally, an aluminum oxide layer on top of the silicon dioxide acts as a glue between the silicon and radio-frequency components. In a process called direct wafer bonding, the researchers stuck the two materials together at 200 °C, well below the temperature at which silicon circuits degrade.

The silicon circuits showed the same performance after integration as before. The radio-frequency transistors showed a record-high unity power gain cutoff frequency—a metric that scales with a device’s possible operating frequencies—of 742 GHz. Other state-of-the-art devices are in the range of 200 to 300 GHz.

At least one other researcher is skeptical of the new device’s viability. Jesús Del Alamo, a micro- and nanoelectronics engineer at the Massachusetts Institute of Technology, says the main problem with this process is that the size of the indium phosphide wafer that contains III-V circuits doesn’t match the silicon wafer below. Standard silicon wafers are 200 or 300 mm in diameter, whereas InP wafers are only 75 or 100 mm. “I think this is a fundamental barrier for this process to be manufacturable in a cost-effective manner.”

Del Alamo says that Intel has overcome the mismatch by growing gallium nitride transistors on silicon wafers, then transferred them to silicon circuitry. The authors of the new work, however, say it should be possible to scale up their III-V process to match the silicon.

Other researchers are working along the same lines as the new work. IBM Research in Zurich says its researchers have also used direct wafer bonding to transfer separately built III-V devices onto silicon substrates and show that it can scale up in size. IBM says the process can also be used to place other types of materials, such as crystalline oxides, onto silicon wafers.


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