A process that’s akin to using a belt sander to smooth a piece of wood might seem like an unlikely area of growth in the high-tech world of semiconductor manufacturing. But growth is exactly what suppliers of materials for this step in manufacturing computer chips, called chemical mechanical planarization, anticipate.
Chemical mechanical planarization, or CMP, smooths successive layers of circuitry on a silicon wafer with the help of a polymer-based pad and a polishing slurry that contains abrasives and other ingredients. Something of a dark art, CMP is so good at creating ultraflat surfaces that it has insinuated itself deeply into the chip-making process.
CMP emerged in the late 1980s as a means of planarizing bare silicon wafers, which are the starting point for semiconductor fabrication. Industry executives see continued growth for the technique as chip architecture keeps shrinking and planarity becomes increasingly important in other corners of the electronics industry. “CMP has matured, but it’s by no means a mature industry,” says Ethan S. Simon, director of CMP R&D at Dow Chemical.
CMP was developed by IBM and Cabot Corp., a producer of the fumed silica particles that were the main abrasive in the first slurries. The field is dominated by two companies: Cabot Microelectronics, a Cabot Corp. spin-off, is the largest slurry manufacturer, and Dow, thanks to its acquisition of Rohm and Haas, is number one in CMP pads. Linx Consulting, which specializes in electronic materials, estimates Dow’s pad market share to be as high as 90%.
But CMP is a global business with dozens of participants making slurries, pads, cleanup compounds, and other polishing consumables. Notably, Dow has a fast-growing slurry business, and Cabot Micro calls itself the number two manufacturer of CMP pads.
Like most businesses related to the electronics industry, CMP was chastened by the recession. Last year, global sales of CMP consumables fell 13% from their 2008 peak of $1.4 billion, according to Linx. Mike Corbett, a Linx managing partner, expects sales to rebound to $1.3 billion this year and then regain their predownturn heights by 2011.
Perhaps the only upside to the recession is the downtime it allowed. In the go-go years before the economy tanked, it took almost all available chip-making capacity to meet demand from manufacturers of computers and other electronic gadgets. The lull freed up polishing tools, Dow’s Simon notes, so customers could try new CMP products and processes.
And new products and processes abound. After debuting on bare silicon wafers, CMP was next applied to silicon oxide, a dielectric material that insulates circuit lines from one another. Then came polishing tungsten, a metal used as an interconnecting wire in multilevel chips. Steven R. Smith, Cabot Micro’s vice president of marketing, says CMP really took off in the early 2000s, when logic-chip makers, including Intel and IBM, switched from using aluminum to using copper as the main metal for circuit lines in their most advanced products.
By Smith’s reckoning, the fabrication of chips with 180-nm-wide aluminum circuit lines, launched in 1999, involved between 12 and 15 discrete CMP steps. Today’s leading-edge logic chips, 32-nm copper-based products, require more than 30 CMP steps. Similarly, as memory chips have shrunk over the past five years, manufacturers have tripled their per-wafer spending on CMP consumables, Smith estimates.
Copper wiring is created by electrodepositing the metal over a network of narrow trenches and holes etched into a dielectric material. Copper is an enticing market for CMP suppliers because two or even three slurries are required for cleanup after its deposition. A “bulk” slurry quickly removes most of the excess copper. A “barrier” slurry then goes farther, sanding down into the copper, the dielectric, and a tantalum barrier layer at an equal rate. Sometimes, a transitional “soft landing” slurry is applied in between.
As copper technology becomes mainstream and proliferates through multiple layers of the chip, it is determining the winners and losers in CMP. For example, DA NanoMaterials, a 10-year-old joint venture between DuPont and Air Products & Chemicals, attributes much of its growth to success in copper polishing, according to Nicholas J. Robertson, the venture’s chief operating officer. “If you win in copper, it has an immediate impact,” he says.
Similarly, Cabot Micro’s historic strengths are in dielectric and tungsten polishing, and its initial foray into copper was in bulk copper removal. Now, Smith says, Cabot Micro is making inroads in the barrier market. On the other hand, PPG Industries dropped out of CMP in 2008 after failing to make appreciable headway in copper.
Copper’s appearance on the scene also marked the start of the fragmentation of the CMP business into smaller, more customized segments, notes Robert L. Rhoades, chief technology officer at Entrepix, a Tempe, Ariz.-based provider of CMP outsourcing and equipment services. That’s because whereas the parameters for dielectric polishing are pretty uniform across the industry, he says, one firm’s copper scheme can be completely different from another’s.
Customization is accelerating with even more advanced generations of chips. “As different companies adopt new materials—hard masks, cap layers, dielectrics, et cetera—it’s no longer a one-size-fits-all CMP world,” Rhoades says.
Indeed, several other new CMP markets are beckoning, say marketers and researchers in the business, although none has the demand potential of copper. One example, Linx’s Corbett notes, is the hafnium-containing transistor gate that debuted in 45-nm logic chips and is also in the new 32-nm devices.
Elsewhere in the chip, new barrier materials are also demanding new polishing techniques. For example, as dimensions shrink, tantalum barriers are reaching their functional limits, says Saifi Usmani, vice president of marketing and technology at DA Nano. Semiconductor fabricators are considering barriers based on ruthenium, but this metal’s hardness presents a challenge to the polishing community.
Yet another potential CMP market, Dow’s Simon notes, is for channels known as through-silicon vias, or TSVs. These minuscule holes punched through a chip’s underlying silicon enable it to be hooked up with other chips in a space-saving architecture. The circuit is completed by filling the tiny holes with copper. TSVs promise a lucrative CMP opportunity, Simon explains, because their creation leaves a thick excess of metal that must be polished away.
Even outside the semiconductor industry, CMP is making a mark, Entrepix’ Rhoades points out. One example is micro-electro-mechanical systems, or MEMS, which are tiny moving devices created with lithography, chemical vapor deposition, and other tools commonly associated with the chip industry. Measured in micrometers instead of nanometers, the features in MEMS are much larger than those in semiconductors and thus require considerable polishing to be made planar, Rhoades notes.
To keep up with customers who want to use CMP in new applications, chemical companies must develop new materials that do the job. For example, the fumed silica in the original slurries is giving way to other abrasives. A new report from Linx points out that today’s slurries can contain particles of aluminum oxide, colloidal silica, cerium dioxide, and even specially engineered particles with inorganic and polymeric elements.
But as circuitry goes beyond 32 nm to 22 nm or even to 15 nm in the future, abrasives can cause lethal microscratches on a wafer’s surface. DA Nano, for one, is cutting the amount of abrasives in its slurries, Usmani says.
In their place, the firm is emphasizing other ingredients such as surfactants, polymers, and various organic and inorganic materials. “Those abrasives we do use must be well controlled and tailored,” he says, noting that DA Nano runs its own colloidal silica plant in the U.K.
Dow formulates most of its slurries with colloidal silica it obtains through a partnership with AZ Electronic Materials. But some of Dow’s customers are now sampling abrasive-free slurries that came out of a joint development agreement with IBM, Simon notes. Dubbed Reactive Liquid Products, the slurries can polish copper without the hollowing out and scratching that traditional CMP slurries can cause, he says.
Its roots notwithstanding, Cabot Micro isn’t wedded to fumed silica, Smith points out. Many of the firm’s recently developed slurries contain fewer abrasives, but he questions the ability of abrasive-free slurries to meet customer needs for low defects, good wafer topography, and high removal rates. “We believe you need an appropriate combination of abrasive and chemical action to meet these requirements,” Smith says.
Cutting abrasive content can also reduce the cost of slurries, a welcome development for customers that are using as much as $20 worth of slurry per wafer that they build. Simon says Dow’s CMP researchers have been trying to understand the fluid hydrodynamics of the polishing process. One outcome, he explains, is a line of pads that can help customers cut slurry consumption by as much as 20%.
Likewise, one goal of Cabot Micro’s pad development effort, Smith says, is to reduce CMP costs by extending pad life. The key to the firm’s D100 pads, introduced in 2007, is that they are made of a thermoplastic polyurethane, not the typical thermoset polyurethane. Cabot Micro’s D200 pads, now being tested by customers, have the added benefit of being easily adjusted for hardness, pore size, and porosity, depending on the application, Smith says.
Prices of CMP consumables are indeed coming down, according to Corbett. Linx estimates that slurries cost about $6.00 per gal at their point of use today, down sharply from $18 per gal just five years ago. Pad prices have fallen less precipitously, although pad longevity has improved, Corbett adds.
But the business is still quite profitable—Cabot Micro had an enviable 50% gross profit margin in its fiscal first half—and it is still growing, despite the similarity to belt-sanding that some might find unsettling. “CMP will continue to grow faster than the general electronic materials space,” DA Nano’s Robertson says. “More and more layers will need to be polished as chip technology shrinks.”