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Large Wafers And Extreme Light

The microchip industry is preparing for two big production technology shifts

by Jean-François Tremblay
April 15, 2013 | A version of this story appeared in Volume 91, Issue 15

Credit: IMEC
Scientists at the Imec research consortium in Belgium set up an EUV lithography scanner in their clean room.
ASML equipment for extreme ultraviolet lithography of semiconductors in the process of being set up at IMEC labs in Belgium.
Credit: IMEC
Scientists at the Imec research consortium in Belgium set up an EUV lithography scanner in their clean room.

They’re both years late, but two long-awaited manufacturing changes are finally nearing implementation in the semiconductor industry. One is the processing of much larger silicon wafer disks, which will reduce the cost of making individual chips. The other is a shift to lithography based on extreme ultraviolet (EUV) light as a method for patterning dense chip circuitry.

Chemical companies that manufacture materials used in electronics will play a big role in implementing the changes. The increase in wafer size to a diameter of 450 mm from the current 300 mm brings only modest technical challenges. The introduction of EUV is trickier but doable.

The problem is that the old techniques are not going away. Chemical companies are not looking forward to having to support multiple customers on multiple technology platforms—all at the same time.

On the face of it, materials suppliers have had plenty of time to get ready for bigger wafers and EUV. In 2008, conventional wisdom was that 450-mm wafers would become a market reality in 2012. As for EUV, it’s been expected even longer. The industry’s “road map” predicted 10 years ago that EUV would become commercially practical in 2009.

EUV’s implementation has been delayed because of difficulties developing the proper source of low-wavelength light. As for the larger silicon wafers, the holdup there is the huge capital investment required.

It will be 2018 before widespread commercial adoption of 450-mm wafers and EUV lithography will take place, according to Nobu Koshiba, president of the Japanese rubber and electronic materials maker JSR. “It will be almost at the same time,” he says.

A caveat, Koshiba adds, is that commercial adoption and “early” adoption are two different things. As early as 2014 some semiconductor manufacturers may be using EUV for selected parts of next-generation logic chips featuring circuitry on the 14-nm scale—compared with the 22-nm circuit lines that are cutting edge today.

“When the chip makers start implementing EUV, they will be running two different processes in parallel,” Koshiba explains. “This will allow the engineers and the fabricators to get used to EUV.”

It’s a similar story for 450-mm wafers. The chip giant Intel is likely to begin processing the larger wafers before its competitors do, Koshiba speculates, stressing that this is not based on inside knowledge of Intel. Last summer, Intel invested about $4 billion in the semiconductor manufacturing equipment supplier ASML. Intel said at the time it wanted to support ASML’s development of 450-mm wafer technology as well as EUV lithography.

Although timetables are clearly fluid, announcements from the electronics industry demonstrate that implementing the two new technologies is a high priority. At the International Solid-State Circuits Conference in February, ASML revealed that a prototype EUV scanner had delivered light pulses at the 60-W level. This is close to commercial scale, according to Jim Fahey, global business director for semiconductors at Dow Electronic Materials. “Once the power source reaches 100 W and beyond, it will no longer be the roadblock and EUV is more feasible ,” he says.

Dow professes to be all set for the arrival of EUV. “We have all the materials ready for customization, including photoresists, antireflective coatings, underlayers and top layers, as well as the chemical mechanical planarization slurries and pads,” Fahey says.

A bigger challenge than being ready, he observes, is knowing what to be ready for. EUV has been delayed so long that it’s not clear whether the new technology will kick in for 14-nm or 7-nm circuitry, the next nodes on the technology development master plan that chip makers are following. Chemical companies need to know, Fahey says, because the materials they supply will be different depending on the circuitry.

Similarly, Shin-Etsu Chemical, the world’s largest producer of silicon wafers, is getting ready for production of 450-mm wafers. “We are carrying out the basic technological development for 450-mm wafers at our research center, and we are shipping samples when we receive inquiries,” a spokesman tells C&EN.

But the company is still unsure whether 2018 will be the year the wafers truly enter the mainstream. “We do not know at what point in time market demand will become large enough nor what kind of product quality will be required,” the spokesman adds.

The electronics industry is adopting the new technologies because they offer a path toward making ever-more-functional electronic devices at an affordable price.

“The fact that someone can buy an iPhone for a few hundred dollars rather than a few million dollars—it’s because we have the ability to generate a lot of computing power at a reasonable cost,” Dow’s Fahey says. “The low cost is partly the result of scaling the circuitry and partly the result of manufacturing efficiencies like the larger wafer sizes.”

The 450-mm wafers offer more than double the surface area of the 300-mm wafers that are now the industry standard. But semiconductor manufacturers must collectively pour several billion dollars into their factories before they can accommodate the larger disks. Although the cost of making a single chip will eventually drop as a result, the enormous capital expenditure has slowed adoption of the new wafers.

Credit: IEEE
Self-aligned double patterning, one of several multiple-patterning techniques, increases circuit line density.
Shown is a diagram of a self-aligned double patterning technique for lithography that increases pattern density.
Credit: IEEE
Self-aligned double patterning, one of several multiple-patterning techniques, increases circuit line density.

“Our customers will have to retool everything in their plants to handle the larger wafer sizes,” says Catherine Markham, R&D director for Dow Electronic Materials. “It’s a capital investment challenge, not a question of whether the industry can do it.”

For electronic materials suppliers, the implementation of 450-mm wafers will require only a modest adjustment to the photoresists, antireflective coatings, and other products they sell to the semiconductor industry.

“If we look at when the industry migrated from 200 mm to 300 mm, we find that coatings that worked perfectly well on a 200-mm wafer worked well for the first 200 mm of the 300-mm wafer but fell apart farther out,” says Ralph R. Dammel, chief technology officer at AZ Electronic Materials, of events that took place about 10 years ago. “We did not have to reinvent the chemistry, but we had to tweak the formulation.”

AZ specializes in ancillary chemicals to support semiconductor lithography including antireflective coatings, photoresist developers and strippers, and anticollapse rinses.

Developing new materials for EUV lithography is more complex than customizing existing ones for larger wafers, but it is not an overwhelming challenge. “We know that our line of materials is looking really good, whenever EUV is ready for prime time,” Dow’s Markham says. The problem is that EUV is not quite ready for prime time. And when it is, the current lithographic methods will still be required for years to come.

Chipmakers will continue to rely on the devilishly complex manufacturing techniques they use today for their older-generation chips and even parts of their latest chips. That process involves spinning a polymer-based photoresist onto a silicon wafer and then patterning circuit lines by shining 193-nm light, generated by an argon fluoride laser, through a photomask.

Coaxing 193-nm light to draw 22-nm circuit lines requires chip makers to adopt so-called multiple-patterning techniques. That involves creating twice or more the usual number of lines on a surface via the single exposure of a dual-tone ­photoresist or multiple exposures of the same photoresist using different photomasks. It’s a manufacturing technique that involves a considerable amount of materials science.

“A multiple-patterning ­solution is a material-intensive solution, whereas achieving a shrink in the circuitry by changing the wavelength of light is a capital-intensive solution,” Markham says.

And although the semiconductor industry expects to push 193-nm lithography to create 14-nm circuits, 193-nm light already reached its theoretical limits years ago, Dammel points out. If 193-nm can still be used, it’s only because the industry has mastered multiple patterning, he adds. “EUV can resolve all that, but it’s been delayed so much that we might have to implement double patterning using EUV soon, and that is a very frightening prospect.”

Faced with this prospect, AZ is championing directed self-assembly (DSA) as an alternative to optical patterning that can work with EUV and in the meantime further pushthe limits of what193-nm lightcan accomplish. In it, blocks of polystyrene and polymethyl methacrylate are guided into assembling themselves by patterns on the wafer surface. DSA could be cheaper and more predictable than a new EUV light source, Dammel contends. In addition, DSA can be used with both EUV and standard 193-nm light to create patterns down to the 7-nm scale, he says.

JSR is also pursuing DSA. The main problem materials suppliers face at the moment, Koshiba says, is not developing materials to support 450-mm wafers, EUV lithography, or even DSA. The problem is that all these new manufacturing techniques could be in use at the same time, straining the technical support capabilities of materials suppliers.

For instance, Koshiba expects memory chip companies to adopt EUV lithography ahead of logic chip firms. On the other hand, logic chip developers will likely move to 450-mm wafers before memory chip makers. And when EUV enters the commercial implementation phase, multiple patterning of silicon wafers with 193-nm light will continue.

“In the past, we talked about a simple shift from argon fluoride laser to EUV, something that would allow us to shift our R&D accordingly,” Koshiba says. “But there are several directions for us to follow at the same time, which makes it hard to use our R&D efficiently.”

Chemical company consternation aside, successful commercial implementation of EUV and 450-mm silicon wafers will help the semiconductor industry stay true to Moore’s law, a 1965 prediction made by Intel cofounder Gordon Moore that the number of transistors on a chip doubles every two years.

At AZ, Dammel says it’s normal for the electronics industry to be uncertain about how to comply with Moore’s law, but it always succeeds. “The industry usually doesn’t know where it’s really going,” Dammel says. “But this time, there is probably more uncertainty than in the past.”


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