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Electronic Chemical Makers Help Keep Gordon Moore’s Prediction Alive

Materials for photolithography, atomic layer deposition, and chemical mechanical planarization aid semiconductor miniaturization

by Alexander H. Tullo , Michael McCoy , Jean-François Tremblay
July 6, 2015 | A version of this story appeared in Volume 93, Issue 27


An Intel wafer containing 14 nm chips.
Credit: Intel
Chemistry is essential to the creation of the modern computer chip.

Aeons from now, people might regard the semiconductors in our computers, phones, and flash drives the same way we now marvel at the Pyramid of Cheops: as wonders of precision and craftsmanship.

Bob Roberts, an industry veteran who works for Axus Technology and also consults for Techcet, tells people to imagine a 12-inch silicon wafer blown up to a mile in diameter. The wafer, at that scale, would be 13 feet thick. But the dozens of complex layers of circuitry that make up the chips on top of it would add less than a quarter of an inch more.

This nanoscale architecture is a feat of collaborative engineering. For 50 years, the semiconductor industry has been marching to a beat set by Gordon E. Moore, the chemist who predicted that the number of transistors on a chip would double every two years. Since then, chemists, physicists, and electrical engineers from a wide range of companies and other institutions have been working in concert to achieve a new “node” of miniaturization every two years, in fulfillment of Moore’s prediction.

Nowadays, leading-edge chips in production, such as those made by Intel, include features as small as 14 nm. The industry is working on chips with parts ever closer to atomic scale. Experimental chips measure in at 10 nm, and features as small as 5 nm are thought to be attainable.

But this won’t happen without more help from chemists and other scientists. This week, C&EN’s business department offers a package of articles about the challenges that semiconductor manufacturers face in shrinking features beyond 10 nm.

To get to 5 nm, fabricators will need to use shorter-wavelength light than the 193-nm ultraviolet light they use today to draw chip features. Senior Correspondent Jean-François Tremblay looks at the delay in arrival of the next generation of light, extreme ultraviolet, and how chipmakers are improving lithography in the meantime.

Once the features are drawn, conducting and insulating materials must be applied in incredibly thin and uniform layers. Assistant Managing Editor Michael McCoy reports on how atomic layer deposition is taking off as a new means of creating those films.

Between manufacturing steps, wafers need to be flattened and cleaned. Senior Correspondent Alexander H. Tullo writes about the challenges facing chemical mechanical planarization as chips become more sophisticated.

Jump to Topics:
- Lithography At The Edge Of Light
Uncertainty around new exposure tools based on extreme ultraviolet technology forces suppliers to pursue multiple research themes
- Fat Opportunity In Thin Films
Semiconductor industry seeks new precursors to deposit atom-thick critical materials
- Chip Polishing Shines Bright
Suppliers of chemical mechanical planarization materials say they are still playing a role in the evolution of chip making


Lithography At The Edge Of Light

Uncertainty around new exposure tools based on extreme ultraviolet technology forces suppliers to pursue multiple research themes

A diagram showing a lithography process.
Credit: Ku Leuven/Advanced Micro Devices
Features are added to semiconductors through multiple photolithographic patterning steps.

These three processes are essential to creating a semiconductor chip. Unless chemists can continue improving them, Moore’s prediction won’t hold up much longer.

In April, photolithography tool manufacturer ASML announced that it was delivering 15 of its extreme ultraviolet (EUV) light exposure systems to one of its customers, probably Intel. The following month, Japanese electronic materials supplier JSR said it was looking to set up a joint venture with a European research group to develop EUV photoresists. The technology has been anticipated for years but delayed because it relies on an extremely powerful 13.5-nm light source.

The two pieces of news seemed to signal that EUV photolithography is finally—albeit years behind schedule—becoming a reality on the shop floor of semiconductor manufacturers. But nothing is straightforward these days as far as semiconductor lithography is concerned. ASML may have stepped up deliveries of its newest tools, and JSR and other specialty chemical companies may be getting ready to support EUV, but it’s far from foregone that the technology is entering the mainstream.

Just as they have been doing for the past several years, producers of electronic materials are scratching their heads over where to invest their R&D dollars. Although EUV seems to be entering the commercial realm, it’s still unclear how widely the technology will be used. To remain competitive, chemical companies are forced to develop a plethora of lithographic materials that their customers may or may not find helpful.

“EUV has made a lot of progress, but it is still not a very economical technique; only a few chipmakers will be able to afford it,” says Ralph R. Dammel, head of the U.S. technology office at Merck KGaA. In recent years, Merck—via AZ Electronic Materials, which it acquired in 2014—has been conducting research on materials that support EUV lithography. But the company has also developed materials used with the current UV light source as well as for other emerging lithographic methods. “The future of patterning is unclear,” Dammel opines.

Patterning refers to the drawing of lines on a silicon substrate to serve as guides for circuits. In lithography, photoresists are coated on a substrate that is later exposed to light, in a process similar to photography, through a photomask. After development, exposed photoresist is stripped from the device surface. Integrated circuits nowadays are made up of as many as 50 layers, each of which needs to go through a lithography process at least once.

According to Moore’s law, a prediction that Intel cofounder Gordon E. Moore made in 1965, the number of transistors that fit on a computer chip doubles every two years. Since then, the electronics industry has followed his prediction as if by legal obligation. The result of this constant shrinking is that integrated circuit manufacturers are producing chips with features only 14 nm wide. Leading firms such as Intel and Samsung are studying how to make chips with features 10 nm or smaller.

To make patterns on such a small scale, the industry requires light sources with short wavelengths. Today’s light source, delivered by an argon fluoride laser, has a 193-nm wavelength. Immersing it in water, which has a higher refractive index than air, lowers the wavelength to 132 nm and allows chipmakers to draw 32-nm lines.

Another trick, called multiple patterning, is being used to draw circuit lines smaller than 32 nm. It’s a collection of techniques for doubling, tripling, or even quadrupling circuit density by overlaying one lithographic pattern on top of another. The method is material-intensive because photoresists and other materials are applied and stripped from the silicon substrate before and after each exposure.

For materials suppliers, multiple patterning is wonderful because each additional exposure boosts their sales. “The more coating operations customers have to do, the more material we sell,” Merck’s Dammel says. “However, multiple patterning is terrible for our customers since their costs are exploding; the industry has to find a better solution.”

But beyond immersion and multiple patterning, the semiconductor industry is running out of ideas on how to keep on using 193-nm light. EUV light, which is only 13.5 nm, could be a solution. But ASML, the only supplier of EUV tools, has struggled to overcome the complex technical issues associated with generating and channeling EUV photons.

When it does arrive, EUV will be a challenge for materials suppliers to support. Until now, leading companies have been able to run production lines in their labs to re-create the manufacturing environment of their customers. At Fujifilm, scientists are manning immersion lithography tools 24 hours a day, says Keiji Mihayashi, president of Fujifilm Electronic Materials.

“If anything bad happens to a customer’s production line, we need to analyze quickly and propose solutions,” he says. It’s unacceptable for a major customer such as Intel, Taiwan Semiconductor Manufacturing Co., or Samsung to stop a production line in which it has invested billions of dollars for any length of time because a material doesn’t perform as expected, Mihayashi adds.

Credit: Dow
A worker prepares wafers for lithography at a Dow semiconductor production line in Marlborough, Mass.
Someone loading wafers into the stacker as it goes into the Lithius tool in Dow’s fab in Marlborough, MA.
Credit: Dow
A worker prepares wafers for lithography at a Dow semiconductor production line in Marlborough, Mass.

But EUV exposure tools such as the ones ASML shipped cost about $100 million apiece and are too expensive for materials producers. Although its main R&D lab is in Shizuoka, Japan, Fujifilm works with the European semiconductor consortium IMEC to develop EUV materials. Through an agreement with ASML, IMEC runs an EUV tool in its labs in Belgium. “If we move on to the manufacturing of EUV photoresists, the question will come up of whether we should conduct manufacturing in Europe as well,” Mihayashi says. At present, Fujifilm produces its most advanced photoresists in Japan.

JSR managers have already decided to establish all their EUV R&D and manufacturing in Belgium. Mitsunobu Koshiba, president of the Japanese firm, explains that the move goes against the grain for JSR. In recent years, the company had successfully centralized its research and manufacturing for electronic materials in Yokkaichi, Japan, where it has invested in a clean-room environment for testing materials. Older generations of photoresists are still made outside Japan.

“The EUV exposure tool is so expensive to buy, so expensive to install, and so expensive to maintain that we cannot afford to do it by ourselves,” Koshiba says. Staff from Yokkaichi will go to Europe to support their European colleagues at a JSR site in Belgium during the start-up of production of EUV resists.

That JSR is committing to EUV resist production, however, doesn’t mean that its managers believe that EUV is becoming an industry standard anytime soon. Initially, Koshiba reckons, the technique will run in parallel with other lithography methods to draw 10-nm features. Later, EUV will be necessary to draw features in the 5-nm range, Koshiba forecasts. By then, he expects that advancement in scaling will be slower and that Moore’s law may no longer be achievable.

Regardless of the lithographic approach, successful materials makers are those that help their customers increase transistor density in an economical manner, managers at those companies say. Catherine Markham, Dow Chemical’s global R&D director for electronic materials, notes that in some cases, multiple patterning may be the most cost-effective solution.

“Dow is not tied to any particular technology and has approaches for directed self-assembly (DSA), multiple patterning, and EUV,” says her colleague Robin Fahey, Dow’s marketing director for lithography. “We are focused on helping our customers to reduce their overall costs, and we develop technologies to achieve that.”

For several years now, scientists at firms such as Dow and Merck have encouraged chip manufacturers to look at DSA as another way to implement Moore’s law at 10 nm and beyond. The technique involves using patterns on a silicon wafer surface to guide blocks of polystyrene and polymethyl methacrylate into assembling themselves.

Materials suppliers have little clout when it comes to convincing customers of the advantages of what they sell. “It’s a dangerous proposition to try to teach the customers their business,” Dammel notes. Still, interest in DSA is rising, he says, judging by how many papers discuss it in journals.

These days, in addition to researching EUV, multiple patterning, and DSA, most major materials suppliers are looking at whatever alternatives are out there. For instance, Fujifilm is studying nanoimprint lithography, a technique explored by Toshiba and Canon. Researching so many technologies is costly, but materials suppliers claim to have little choice. “If a major customer requests us to develop a particular type of material, we must proceed,” Fujifilm’s Mihayashi says.

Another challenge, Mihayashi notes, is the logistics of conducting R&D. Similar to JSR, Fujifilm has centralized its electronic materials research at a lab in Shizuoka, where the company’s most expensive equipment is located. But Fujifilm scientists also need to operate at clients’ sites around the world or to travel frequently to those sites. EUV will further decentralize Fujifilm’s R&D efforts if the company decides it has to conduct more research in Belgium.

Senior managers at electronic materials suppliers bemoan their high R&D outlays. Developing photoresists has become so expensive that only a handful of players recover their costs these days, they say. But the protests may be exaggerated because the investments appear to be paying off. In Japan, for instance, electronic materials suppliers are among the most profitable chemical companies. According to Mihayashi, once a supplier establishes itself as a leader in a particular area, maintaining that position is relatively easy.


Fat Opportunity In Thin Films

Semiconductor industry seeks new precursors to deposit atom-thick critical materials

At Dow, R&D Director Markham is confident that whether it’s in EUV, DSA, or other lithographic technology, little of the research will be wasted. EUV and DSA may well end up coexisting on factory floors at various stages of the manufacturing of the same integrated circuit. “It’s not a question of a yes or a no on DSA,” she says. “Each technical approach eventually finds its home.”


One sign of a hot business is a small company getting acquired by a big competitor. That’s what happened in 2013 when the electronic chemicals maker Voltaix was purchased by Air Liquide.

Perhaps an even clearer sign of a hot business is a small company getting an investment from a big customer. That’s what happened six weeks ago when the electronic chemicals maker Digital Specialty Chemicals received a cash injection from the chip-making giant Intel in exchange for an equity ownership stake.

Voltaix and Digital are both makers of organometallic and organosilane precursors used to deposit thin films during the semiconductor fabrication process. And thin films are hot. As more and more transistors are packed into chips, following the path predicted by Intel cofounder Gordon E. Moore, manufacturers increasingly need the precursors provided by Voltaix, Digital, and other chemical companies to enable further scaling as well as brand-new transistor designs.

They weren’t always required. In the semiconductor industry’s early days, many computer chip functions could be handled by aluminum wires embedded in silicon dioxide on top of a silicon wafer. But as chips got more powerful and circuit lines shrank, aluminum was replaced by copper, and thin layers of supporting materials started to be added.

At first, the films were applied mainly by physical vapor deposition, a technique involving high-temperature vacuum evaporation and condensation of metals.

Later, a newer technique called chemical vapor deposition (CVD) moved in. In CVD, precursor molecules are heated and vaporized. They then flow into a reaction chamber where, often mixed with other reactants, they hit the wafer, release their organic ligands, and end up as a thin inorganic film.

Today, a technique called atomic layer deposition (ALD) is taking center stage. The precursor molecules used in ALD are designed so that only one layer chemically bonds to the surface they land on. The deposition is then repeated multiple times. The result is incredibly thin and uniform layers with high aspect ratios—perfect for making computer chips as small as they can be.

ALD was first used in semiconductor fabrication roughly a decade ago, according to Michael Corbett, an analyst with the electronic materials advisory firm Linx Consulting. That was when dynamic random-access memory (DRAM) chip manufacturers in South Korea started using the precursor trimethylaluminum to apply thin layers of aluminum oxide to create high-dielectric-constant capacitor films.

Since then, Corbett says, the capacitor dielectric material has evolved into oxides of hafnium, zirconium, and now a zirconium/aluminum laminate.

Credit: Air Products
A worker assembles a chemical delivery system at Air Products’ Allentown facility.
A worker at Air Products Allentown, Pa., facility.
Credit: Air Products
A worker assembles a chemical delivery system at Air Products’ Allentown facility.

In logic chips of the type that power laptops and smartphones, ALD was first used about eight years ago to deposit hafnium as a high-dielectric-constant transistor gate oxide. It next found application in work function adjustment, which involves applying a material to equalize the work function—the minimum amount of energy needed to remove an electron—of two metals.

Today, ALD is being deployed throughout the computer chip at a rapidly increasing pace. By Linx’s estimate, the global market for organometallic and organosilane ALD precursors was worth about $325 million last year and should jump almost $100 million this year alone. Linx expects it to approach $1 billion by 2019.

One new application is as a spacer in a process known as self-aligned multiple patterning. Surésh Rajaraman, global business director for advanced deposition materials at Air Products & Chemicals, explains that multiple patterning is an example both of the growing utility of ALD and of how the semiconductor industry solves the seemingly intractable problems that arise as chip geometry shrinks.

Computer chip circuit lines have long been created by shining light through a mask that selectively exposes a photosensitive polymer. The 193-nm light used today can create features that are at best about 40 nm wide. The chip industry is feverishly working on an extreme ultraviolet light source that has a wavelength of just 13.5 nm, but it’s not ready yet.

In the meantime, the industry has turned to multiple patterning, a collection of techniques for doubling, tripling, or even quadrupling circuit line density by overlaying one lithographic pattern on top of another. With multiple patterning, chipmakers such as Intel and Taiwan Semiconductor are getting ready to commercialize chips with 10-nm features and are looking ahead to the single digits.

Air Products comes in as the developer of a precursor for SiO2 used as a sacrificial layer in the multiple-patterning process. According to Rajaraman, the right precursor had to be highly reactive and yet stable at low temperatures. “We needed to be able to put it on containers and ship it globally,” he recalls.

Working with Tokyo Electron, a Japanese manufacturer of semiconductor manufacturing equipment, Air Products scientists sifted through numerous potential precursors and concluded that a monoaminosilane would provide the necessary high reactivity. They then tested multiple ligands to find one that would provide steric hindrance for good stability. The result was diisopropylaminosilane, an SiO2 precursor the company markets as AP-LTO 520.

The research capabilities required to develop and test an ALD precursor such as AP-LTO 520 don’t come cheap, Rajaraman says. At labs in places such as Carlsbad, Calif.; Allentown, Pa.; and Banwol, South Korea; Air Products employs a team of scientists and engineers dedicated to advanced materials for electronics. The firm recently expanded a new-product-development lab in Carlsbad where it operates commercial-scale ALD tools of the type its customers use.

Similarly, Digital Specialty Chemicals will use the funds from Intel to add R&D and manufacturing facilities at its Toronto site, according to Ravi K. Laxman, Digital’s vice president of electronics. For example, it is scaling up a process to produce multiple tons of bis(diethylamino)silane, a competitor to diisopropylaminosilane for SiO2 deposition during multiple patterning.

The firm’s list of investment priorities includes reactors that are dedicated to the electronics industry. Laxman says the company also intends to put more money into R&D and engineering to better understand the costs, environmental impacts, and safety considerations of the organometallic precursors it manufactures, many of which are air sensitive and pyrophoric.

And beyond funding, Digital expects to learn best practices from Intel. “They are extremely good on quality control,” Laxman says. “They can teach us how to do the metrologies and the controls—the techniques of quality management.”

Quality control is growing in importance as purity requirements rise and precursors take on new physical forms. For example, pentakis(dimethylamino) tantalum, or PDMAT, is an organometallic precursor used to deposit tantalum nitride, a barrier layer that keeps copper atoms in chip wiring from diffusing into the surrounding dielectric material. But unlike the gaseous or liquid precursors of the past, PDMAT is a solid at room temperature.

A diagram showing a surface being built up step by step.
Atomic layer deposition is a gas-phase process that lays down single layers of molecules—in this case aluminum oxide—at a time (Al is blue, C is black, O is red, and H is gray).

“As we go to solid precursors,” Rajaraman says, “we have had to establish new test capabilities to understand particle generation. We must figure out how to control delivery rates for these precursors.” Air Products, he adds, has a dedicated container R&D team that develops the containers needed to deliver air- and moisture-sensitive organometallics.

Investments such as these will come into play as chip geometries shrink past the 10-nm mark and ALD’s role becomes even more critical, chemical executives say. Intel and other semiconductor makers are mining the periodic table in search of elements that will help them continue packing circuits and transistors into their chips.

For example, Paul C. Burlingame, chief executive officer of Voltaix, says his firm is working with its semiconductor industry customers to develop manganese-containing precursors for self-forming manganese silicate barriers used to prevent migration of copper. It’s creating liquid precursors based on lanthanide series elements as new work-function-adjusting materials for advanced logic chips.

Voltaix also developed a precursor for depositing the high-dielectric-constant zirconium oxide layer in DRAM chips. “From that initial success we have now added other precursors to our portfolio for future devices, whether next-generation DRAM, flash memory, or new such as ReRAM,” Burlingame says.

Likewise, Digital’s Laxman sees increased use of ALD in a new generation of memory chips that stack memory cells in three dimensions rather than two. These devices will require higher-dielectric-constant films of zirconium oxide or combinations of zirconium oxide and other elements. And because the devices will be made with self-aligned multiple patterning, new low-temperature SiO2 precursors will be needed as well.

The list of potential ALD outlets goes on. Manufacturers of logic devices are adding cobalt layers and caps to enhance existing copper circuitry deposition processes. Precursors for metals such as tungsten, titanium, and aluminum are being used or studied to continue adjusting work function.

ALD isn’t a cure-all for the semiconductor industry. Linx’s Corbett notes that the exotic organometallic precursors required can make the process expensive. And although new batch techniques for treating many silicon wafers at once have helped speed up ALD technology, it is still not as fast as CVD.


Chip Polishing Shines Bright

Suppliers of chemical mechanical planarization materials say they are still playing a role in the evolution of chip making

Credit: Applied Materials
Applied Materials’ Reflexion LK Prime chemical mechanical planarization system is suited for three-dimensional chip fabrication, an emerging area.
Credit: Applied Materials
Applied Materials’ Reflexion LK Prime chemical mechanical planarization system is suited for three-dimensional chip fabrication, an emerging area.

Still, Corbett and others in the field see ALD’s influence growing as more and more of the periodic table is tapped to make computer chips. “As the industry goes down the road map and more elements are introduced to continue scaling and performance gains,” Corbett says, “a lot of those elements will be applied via ALD.”

In 1983, while working as a sales representative for the polishing equipment supplier Strasbaugh, Bob Roberts received a call from a pair of engineers at IBM’s semiconductor plant in East Fishkill, N.Y.

Roberts thought IBM was interested in new grinding machines for processing monocrystalline silicon wafers before circuitry is laid on, a routine operation.


But Big Blue’s engineers actually wanted to polish the surface of the wafer after wires and transistors had been added. Roberts was surprised. “You don’t touch that, you don’t breathe on it because it is so pristine,” he recalls of the prevailing attitude at the time. And here IBM was fixing to attack it with abrasives.

“It was so radical that people were sure IBM had it all wrong,” recalls Roberts, who works for Axus Technology and consults for the electronic materials consulting firm Techcet. He ended up selling IBM what would become the very first chemical mechanical planarization (CMP)machines.

IBM wasn’t reckless. It was merely ahead of its time. As demand for faster chips grew, the transistors and circuit lines on microprocessors were getting smaller. Moreover, layers of circuitry were being stacked on top of one another, with layers of silicon dioxide insulation laid down in between.

As layers were added, the IBM scientists realized, the bumps and imperfections—the topology, in other words—would have to be flattened out, or planarized. If a surface is too bumpy, the lithography process used to draw circuitry on a chip yields blurry images, leading to imprecise lines and defective chips.

In the 30 years since then, miniaturization has progressed and still has yet to reach its fundamental limits. Meanwhile, the number of layers on a chip is still increasing. “In the old days, the wafer went through one time,” Roberts says. “It got one layer of circuitry and then you were done.” Nowadays, that wafer is going through the chip fabrication plant dozen of times.

All this has created enormous demand for the abrasive slurries and polishing pads that chemical companies supply for the CMP process, which according to Techcet is now a $2 billion-per-year business. It has also increased the technical demands made on the slurries and pads. Materials suppliers say it’s a task they are equal to.

One doesn’t need to understand a lot about solid-state physics to get the basic idea behind CMP. “At a top level this is a very simplistic thing, like polishing the hood of your car,” says Colin Cameron, business director of CMP pads for Dow Chemical. “But when you get to the angstrom level of precision required for semiconductor manufacture, it gets very complex.”

CMP slurries are waterborne formulations of abrasives and chemicals. The abrasives are normally particles of ceria, alumina, or colloidal or fumed silica. They wear away excess material from the wafer by “mechanically” scratching it off.

A cocktail of active compounds is responsible for the “chemical” part of CMP. Oxidizers, for example, oxidize metals such as tungsten and copper so they become brittle enough for the abrasive particles to whisk excess away. Corrosion inhibitors prevent pitting in the circuitry. Surfactants regulate the electric charges of the slurry and the wafer surface so the two don’t repel each other.

According to Techcet, Dow has a commanding 78% share of the market for CMP pads, most of which are made of polyurethane. Dow’s Cameron says the porosity and hardness of the pads are tailored depending on what is being planarized and how much the process can tolerate defects. “The softer, more pliable pad materials are generally better for defects but not as good for creating that planarized surface,” he says. “Stiffer materials lend themselves to better planarization.”

When CMP was first used, the widths of circuit lines and transistors could be measured in micrometers. But every couple of years, the industry scales down further. Now, leading-edge semiconductor companies such as Intel are making chips with 14-nm features. In a few years, they will likely be 10 nm. Longer term, the industry could reach 5 nm before encountering fundamental limits that stop the scaling progress for good.

At these small scales, what experts call “defectivity”—the propensity of the CMP process to leave particles and scratches on a chip’s surface—comes into play, and the requirements for the slurry formulations become more exacting, notes Robert Cates, the director of marketing for Cabot Microelectronics.

Purity levels are raised to eradicate errant materials. Particles become smaller so as not to damage fragile architecture. The size distribution of the particles gets tighter. “Early on in CMP, when we were polishing at 180 nm, a given amount of variation was acceptable compared to when you get down to 10 nm,” Cates says.

Cabot, with its fumed-silica-based slurries, helped IBM develop the CMP process. According to Techcet, it is still the leader in slurries with a 36% market share.

A graphic of a disc polishing a larger disc.
Chemical mechanical planarization is a means of smoothing a silicon wafer so additional layers of circuitry can be applied.

Slurry competitor Air Products & Chemicals sees a lot of opportunity ahead at 10 nm for shallow-trench-isolation polishes. Shallow trench isolation, in which insulating materials are applied to trenches to prevent electrical leakage, is becoming increasingly important as transistors get smaller and closer together, says Ed Shober, general manager of the firm’s advanced materials business.

To this end, Air Products has joined the Advanced Planarization Center at the Nanotech Complex, operated in Albany, N.Y., by SUNY Polytechnic Institute’s Colleges of Nanoscale Science & Engineering. At the facility, Air Products will have access to tools and test wafers on which it can prove its shallow-trench-isolation slurries and post-CMP cleaning products. “We’re going to try to accelerate the development of our CMP offerings for those sub-10-nm fabrication steps,” Shober says.

Technology is advancing in polishing pads as well. The latest from Dow is its Ikonic family of pads. Cameron says Dow tweaks polyurethane properties by altering polyols, cross-linkers, and curatives. By making harder pads that planarize while minimizing defects, the company says it circumvents, to some extent, the old trade-off. “Ikonic has been essential to support the CMP requirements associated with 10-nm, 14-nm, and 20-nm processes,” Cameron says.

How low CMP can go is the “billion-dollar question,” according to Air Products’ Shober. “We’re going to move to 10 nm,” he says. “We’ll eventually get some end users at 8 nm and 6 nm and maybe 7 nm and 5 nm.”

Whether that happens quickly is another question. Shober notes that it took the industry nearly three years to get to the 14-nm feature node from 22 nm. “Where the prior industry cadence was that every two years we were moving to a new node, it takes additional time now to advance,” he says.

That isn’t to say chipmakers aren’t making progress. As miniaturization starts to slow, device manufacturers are looking to three-dimensional architectures rather than working only in a two-dimensional plane. The technique, for example, allows memory chip fabricators to cram twice the data into the same amount of space.

Alex Chang, CMP business director at slurry maker Fujifilm, says new architectures translate into opportunity for CMP in the “front end” of the chip manufacturing process, when the transistors are installed on the wafer but before the metals and barrier films of the “back end” are laid on.

In terms of the size of the opportunity, the front end doesn’t yet compare with other applications, such as planarizing copper and barrier layers, that drove the CMP business about a decade ago. “But in the future, I think there is a great potential for the market growth and the business growth,” Chang says.

Cabot’s Cates agrees. “The back end is generally replicated from node to node with some slight adjustments, but it is the front end where they are really changing the architecture and materials,” he says. “That creates a lot of opportunity for slurry and pads. It requires more polishing steps to build the front end of the device.” For example, stacked devices often use “through-silicon vias”—holes in the silicon in which conductors are deposited to connect multiple chips.

The trends are aligning favorably for CMP materials suppliers. They argue that they will continue to play a role in miniaturization. They are also an integral part of emerging 3-D architectures. And Shober sees no real alternative to the CMP process step.


Jump to Topics:
- Lithography At The Edge Of Light
Uncertainty around new exposure tools based on extreme ultraviolet technology forces suppliers to pursue multiple research themes
- Fat Opportunity In Thin Films
Semiconductor industry seeks new precursors to deposit atom-thick critical materials
- Chip Polishing Shines Bright
Suppliers of chemical mechanical planarization materials say they are still playing a role in the evolution of chip making

“It appears that there is no technology on the horizon to replace CMP today as a semiconductor processing application,” he says. “It paints a fairly encouraging picture going forward.”  


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